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WM8706 24-bit, 192kHz Stereo DAC with Volume Control
Product Preview, Rev 1.2, April 2001
DESCRIPTION
The WM8706 is a high performance stereo DAC designed for audio applications such as DVD, home theatre systems, and digital TV. The WM8706 supports data input word lengths from 16 to 32-bits and sampling rates up to 192kHz. The WM8706 can implement 2 channels at 192kHz for highend DVD-Audio. The WM8706 consists of a serial interface port, digital interpolation filters, multi-bit sigma delta modulators and stereo DAC in a small 28-pin SSOP package. The WM8706 also includes a digitally controllable mute and attenuate function on each channel. The WM8706 supports a variety of connection schemes for audio DAC control. The MPU serial port provides access to a wide range of features including on-chip mute, attenuation and phase reversal. A hardware controllable interface is also available. It is pin-compatible with the WM8716 provided the oscillator circuit on WM8716 is not required in the application. The WM8706 is an ideal device to interface to AC-3, DTS, and MPEG audio decoders for surround sound applications, or for use in DVD players supporting DVD-A.
FEATURES
* * Stereo DAC Audio Performance 106dB SNR (`A' weighted @ 48kHz) DAC -97dB THD DAC Sampling Frequency: 8kHz - 192kHz 3-Wire Serial Control Interface or Hardware Control Programmable Audio Data Interface Modes I2S, Left, Right Justified, DSP 16/20/24/32 bit Word Lengths Independent Digital Volume Control on Each Channel with 127.5dB Range in 0.5dB Steps 3.0V - 5.5V Supply Operation 28-Pin SSOP Package Exceeds Dolby Class A Performance Requirements
* * *
* * * *
APPLICATIONS
* * * * DVD-Audio and DVD `Universal' Players Home theatre systems Digital TV Digital broadcast receivers
BLOCK DIAGRAM
MODE MLIIS MCDM1 MDDM0 MUTEB CSBIWO ZERO
CONTROL INTERFACE
WM8706
BCKIN LRCIN DIN SERIAL INTERFACE
MUTE/ ATTEN DIGITAL FILTERS MUTE/ ATTEN
SIGMA DELTA MODULATOR
RIGHT DAC
LOW PASS FILTER
VOUTR
SIGMA DELTA MODULATOR
LEFT DAC
LOW PASS FILTER
VOUTL
VMID
XTI
AVDD DVDD
VREFP VREFN
AGND
DGND
WOLFSON MICROELECTRONICS LTD
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 Email: sales@wolfson.co.uk www.wolfsonmicro.com
Product Preview data sheets contain specifications for products in the formative phase of development. These products may be changed or discontinued without notice.
2001 Wolfson Microelectronics Ltd.
WM8706
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PIN CONFIGURATION
LRCIN DIN BCKIN NC XTI NC DGND DVDD NC NC NC NC VOUTR AGND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 MLIIS MCDM1 MDDM0 MUTEB MODE CSBIWO NC ZERO VREFP VREFN VMID NC VOUTL AVDD
ORDERING INFORMATION
DEVICE XWM8706EDS TEMP. RANGE -25 to +85oC PACKAGE 28-pin SSOP
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PIN DESCRIPTION
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 CSBIWO MODE MUTEB MDDM0 MCDM1 MLIIS VMID VREFN VREFP ZERO VOUTR AGND AVDD VOUTL DGND DVDD XTI NAME LRCIN DIN BCKIN TYPE Digital Input Digital Input Digital Input NC Analogue Input NC Supply Supply NC NC NC NC Analogue Output Supply Supply Analogue Output NC Analogue Output Supply Supply Digital Output NC Digital Input Digital Input Digital Bi-directional Digital Bi-directional Digital Input Digital Input Serial Audio Data Input Audio Data Bit Clock Input. No internal connection Master Clock Input No Internal Connection Digital Ground Supply Digital Positive Supply No Internal Connection No Internal Connection No Internal Connection No Internal Connection Right Channel DAC Output Analogue Ground Supply Analogue Positive Supply Left Channel DAC Output No Internal Connection Mid Rail Decoupling Point DAC Negative Reference - normally AGND, must not be below AGND DAC Positive Reference - normally AVDD, must not be below AVDD Infinite Zero Detect Flag No Internal Connection Software Mode: 3-Wire Serial Control Chip Select Hardware Mode: Input Word Length, Pull Up Control Mode Selection (Low = Hardware, High = Software), Pull Down Mute Control (L = Mute on, H = Mute off, Z = Automute Enabled), Pull Up Software Mode: 3-Wire Serial Control Data Input: Hardware Mode: De-Emphasis Software Mode: 3-Wire Serial Control Clock Input Hardware Mode: De-Emphasis, Pull Down Software Mode 3-Wire Serial Control Load Input Hardware Mode: Input Data Format Selection, Pull Up DESCRIPTION DAC Sample Rate Clock Input
Note: Digital input pins have Schmitt trigger input buffers.
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ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device.
CONDITION Digital supply voltage Analogue supply voltage Voltage range digital inputs Voltage range analogue inputs Master Clock Frequency (XTI) Operating temperature range, TA Storage temperature Package body temperature (soldering 10 seconds) Package body temperature (soldering 2 minutes) Note: Analogue and digital grounds must always be within 0.3V of each other.
MIN -0.3V -0.3V DGND -0.3V AGND -0.3V
MAX +7V +7V DVDD +0.3V AVDD +0.3V 50MHz
-25C -65C
+85C +150C +240C +183C
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DC ELECTRICAL CHARACTERISTICS
PARAMETER Digital supply range Analogue supply range Ground Difference DGND to AGND Analogue supply current Digital supply current Analogue supply current Digital supply current AVDD = 5V DVDD = 5V AVDD = 3.3V DVDD = 3.3V SYMBOL DVDD AVDD AGND, DGND -0.3 TEST CONDITIONS MIN 3.0 3.0 0 0 19 8 18 4 +0.3 TYP MAX 5.5 5.5 UNIT V V V V mA mA mA mA
ELECTRICAL CHARACTERISTICS
Test Conditions AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, XTI = 256fs unless otherwise stated. PARAMETER Digital Logic Levels (TTL Levels) Input LOW level Input HIGH level Output LOW Output HIGH Analogue Reference Levels Reference voltage VMID (VREFP VREFN)/2 50mV (VREFP VREFN)/2 12k At DAC outputs A-weighted, @ fs = 48kHz A-weighted @ fs = 96kHz A-weighted @ fs = 192kHz A-weighted, @ fs = 48kHz AVDD, DVDD = 3.3V A-weighted @ fs = 96kHz AVDD, DVDD = 3.3V Non `A' weighted @ fs = 48kHz 1kHz, 0dBfs 1kHz, -60dBfs 100 1.1 x AVDD/5 106 106 106 105 (VREFP VREFN)2 + 50mV V VIL VIH VOL VOH IOL = 1mA IOH = 1mA AVDD - 0.3V 2.0 AGND + 0.3V 0.8 V V V V SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Potential divider resistance 0dBFs Full scale output voltage SNR (Note 1,2,3) SNR (Note 1,2,3) SNR (Note 1,2,3) SNR (Note 1,2,3)
RVMID
ohms Vrms dB dB dB dB
DAC Output (Load = 10K ohms. 50pF)
SNR (Note 1,2,3)
103
dB
SNR (Note 1,2,3) THD (Note 1,2,3) THD+N (Dynamic range, Note 2) DAC channel separation
106 -97 100 106 100
dB dB dB dB
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Test Conditions AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, XTI = 256fs unless otherwise stated. PARAMETER Analogue Output Levels Output level Load = 10k ohms, 0dBFS Load = 10k ohms, 0dBFS, (AVDD = 3.3V) 1.1 0.726 SYMBOL TEST CONDITIONS MIN TYP MAX
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UNIT VRMS VRMS
Gain mismatch channel-to-channel Minimum resistance load To midrail or a.c. coupled To midrail or a.c. coupled (AVDD = 3.3V) 5V or 3.3V
1 1 600
%FSR kohms ohms
Maximum capacitance load Output d.c. level Power On Reset (POR) POR threshold
100 (VREFP VREFN)/2 2.4
pF V
V
Notes: 1. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured `A' weighted over a 20Hz to 20kHz bandwidth. 2. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. 3. VMID decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance).
TERMINOLOGY
1. 2. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results). Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal. Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB). THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band). Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other.
3. 4. 5.
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MASTER CLOCK TIMING
tXTIL XTI tXTIH tXTIY
Figure 1 Master Clock Timing Requirements Test Conditions AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, XTI = 256fs unless otherwise stated. PARAMETER Master Clock Timing Information
XTI Master clock pulse width high XTI Master clock pulse width low XTI Master clock cycle time XTI Duty cycle
SYMBOL tXTIH tXTIL tXTIY
TEST CONDITIONS
MIN 13 13 26 40:60
TYP
MAX
UNIT ns ns ns
60:40
DIGITAL AUDIO INTERFACE
tBCH BCKIN tBCY tBCL
LRCIN tDS DIN tDH tLRH tLRSU
Figure 2 Digital Audio Data Timing
Test Conditions AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, XTI = 256fs unless otherwise stated. PARAMETER BCKIN cycle time BCKIN pulse width high BCKIN pulse width low LRCIN set-up time to BCKIN rising edge LRCIN hold time from BCKIN rising edge DIN set-up time to BCKIN rising edge DIN hold time from BCKIN rising edge SYMBOL tBCY tBCH tBCL tLRSU tLRH tDS tDH TEST CONDITIONS MIN 40 16 16 8 8 8 8 TYP MAX UNIT ns ns ns ns ns ns ns
Audio Data Input Timing Information
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WM8706 MPU INTERFACE TIMING
CSBIWO tCSSU tCSSH tCSL tCSH
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MLIIS tSCY tSCH MCDM1 tSCL tSCS tCSS
MDDM0 tDSU tDHO
LSB
Figure 3 Program Register Input Timing - 3-Wire Serial Control Mode
Test Conditions AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, XTI = 256fs unless otherwise stated. PARAMETER MCDM1 rising edge to MLIIS rising edge MCDM1 pulse cycle time MCDM1 pulse width low MCDM1 pulse width high MDDM0 to MCDM1 set-up time MCDM1 to MDDM0 hold time MLIIS pulse width low MLIIS pulse width high MLIIS rising to SCLK rising CSBIWO to MLIIS set-up time MLIIS to CSBIWO hold time SYMBOL tSCS tSCY tSCL tSCH tDSU tDHO tCSL tCSH tCSS tCSSU tCSSH TEST CONDITIONS MIN 40 80 20 20 20 20 20 20 20 20 20 TYP MAX UNIT ns ns ns ns ns ns ns ns ns Ns ns
Program Register Input Information
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DEVICE DESCRIPTION
INTRODUCTION
The WM8706 is a high performance DAC designed for digital consumer audio applications. Its range of features make it ideally suited for use in DVD players, AV receivers and other high end consumer audio equipment. The WM8706 is a complete 2-channel stereo audio digital-to-analogue converter, including digital interpolation filter, multi-bit sigma delta with dither, and switched capacitor multi-bit stereo DAC and output smoothing filters. The WM8706 includes an on-board digital volume control, configurable digital audio interface and a 3 wire MPU control interface. It is fully compatible and an ideal partner for a range of industry standard microprocessors, controllers and DSPs. Control of internal functionality of the device is by either hardware control (pin programmed) or software control (3-wire serial control interface). The MODE pin selects between hardware and software control. The software control interface may be asynchronous to the audio data interface. Control data will be re-synchronised to the audio processing internally. Operation using master clocks of 256fs, 384fs, 512fs or 768fs is provided, selection between clock rates being automatically controlled in hardware mode, or serial controlled when in software mode. Sample rates (fs) from less than 8ks/s to 96ks/s are allowed, provided the appropriate master clock is input. Support is also provided for up to 192ks/s using a master clock of 128fs or 192fs. The audio data interface supports right, left and I2S (Philips left justified, one bit delayed) interface formats along with a highly flexible DSP serial port interface. When in hardware mode, the three serial interface pins become control pins to allow selection of input data format type (I2S or right justified), input word length (16, 20, or 24-bit) and de-emphasis functions. The device is packaged in a small 28-pin SSOP and is a pin-compatible alternative to the WM8716.
CLOCKING SCHEMES
In a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronised. This clock is often referred to as the audio system's Master Clock. The external master system clock can be applied directly through the XTI input pin with no software configuration necessary for sample rate selection. Note that on the WM8706, XTI is used to derive clocks for the DAC path. The DAC path consists of DAC sampling clock, DAC digital filter clock and DAC digital audio interface timing. In a system where there are a number of possible sources for the reference clock it is recommended that the clock source with the lowest jitter be used to optimise the performance of the DAC.
DIGITAL AUDIO INTERFACE
Audio data is applied to the internal DAC filters via the Digital Audio Interface. 5 popular interface formats are supported: * * * * * Left Justified mode Right Justified mode I2S mode DSP Early mode DSP Late mode
All 5 formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits. The exception is that 32 bit data is not supported in right justified mode. DIN and LRCIN are sampled on the rising, or falling edge of BCKIN depending on the format selected. In left justified, right justified and I2S modes, the digital audio interface receives data on the DIN input. Audio Data is time multiplexed with LRCIN indicating whether the left or right channel is present. LRCIN is also used as a timing reference to indicate the beginning or end of the data words.
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2
Product Preview In left justified, right justified and I S modes, the minimum number of BCKINs per LRCIN period is 2 times the selected word length. LRCIN must be high for a minimum of word length BCKINs and low for a minimum of word length BCKINs. Any mark to space ratio on LRCIN is acceptable provided the above requirements are met. The WM8706 will automatically detect when data with a LRCIN period of exactly 32 is sent, and select 16 bit mode - overriding any previously programmed word length. Word length will revert to the previously programmed value when a LRCIN period other than 32 is detected. (see Figure 4, Figure 5 and Figure 6). In DSP early or DSP late mode, the data is time multiplexed onto DIN. LRCIN is used as a frame sync signal to identify the MSB of the first word. The minimum number of BCKINs per LRCIN period is 2 times the selected word length. Any mark to space ratio is acceptable on LRCIN provided the rising edge is correctly positioned (see Figure 7 and Figure 8).
LEFT JUSTIFIED MODE
In left justified mode, the MSB is sampled on the first rising edge of BCKIN following a LRCIN transition. LRCIN is high during the left samples and low during the right samples.
1/fs
LEFT CHANNEL LRCIN
RIGHT CHANNEL
BCKIN
DIN
1
2
3
n-2 n-1
n
1
2
3
n-2 n-1
n
MSB
LSB
MSB
LSB
Figure 4 Left Justified Mode Timing Diagram
RIGHT JUSTIFIED MODE
In right justified mode, the LSB is sampled on the rising edge of BCKIN preceding a LRCIN transition. LRCIN is high during the left samples and low during the right samples.
1/fs
LEFT CHANNEL LRCIN
RIGHT CHANNEL
BCKIN
DIN
1
2
3
n-2 n-1
n
1
2
3
n-2 n-1
n
MSB
LSB
MSB
LSB
Figure 5 Right Justified Mode Timing Diagram
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I S MODE
2
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In I2S mode, the MSB is sampled on the second rising edge of BCKIN following a LRCIN transition. LRCIN is low during the left samples and high during the right samples.
1/fs
LEFT CHANNEL LRCIN
RIGHT CHANNEL
BCKIN
1 BCKIN 1 BCKIN 3 n-2 n-1 n 1 2 3 n-2 n-1 n
DIN
1
2
MSB
LSB
MSB
LSB
Figure 6 I2S Mode Timing Diagram
DSP EARLY MODE
In DSP early mode, the first bit is sampled on the BCKIN rising edge following the one which detects a low to high transition on LRCIN. No BCKIN edges are allowed between the data words. The word order is DIN left, DIN right.
1 BCKIN 1/fs 1 BCKIN
LRCIN
BCKIN
LEFT CHANNEL
RIGHT CHANNEL
NO VALID DATA
DIN
1
2
n-1
n
1
2
n-1
n
MSB
LSB
Input Word Length (IWO)
Figure 7 DSP Early Mode Timing Diagram
DSP LATE MODE
In DSP late mode, the first bit is sampled on the BCKIN rising edge which detects a low to high transition on LRCIN. No BCKIN edges are allowed between the data words. The word order is DIN left, DIN right.
1/fs
LRCIN
BCKIN
LEFT CHANNEL
RIGHT CHANNEL
NO VALID DATA
DIN
1
2
n-1
n
1
2
n-1
n
1
MSB
LSB
Input Word Length (IWO)
Figure 8 DSP Late Mode Timing Diagram
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WM8706 AUDIO DATA SAMPLING RATES
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The master clock for WM8706 supports audio sampling rates from 128fs to 768fs, where fs is the audio sampling frequency (LRCIN) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The master clock is used to operate the digital filters and the noise shaping circuits. The WM8706 has a master clock detection circuit that automatically determines the relation between the master clock frequency and the sampling rate (to within +/- 32 master clocks). If there is a greater than 8 clocks error, the interface shuts down the DAC and mutes the output. The master clock should be synchronised with LRCIN, although the WM8706 is tolerant of phase differences or jitter on this clock. SAMPLING RATE (LRCIN) MASTER CLOCK FREQUENCY (MHZ) (XTI) 128fs 192fs 256fs 384fs 512fs 768fs 24.576 33.8688 36.864 Unavailable Unavailable
32kHz 4.096 6.144 8.192 12.288 16.384 44.1kHz 5.6448 8.467 11.2896 16.9340 22.5792 48kHz 6.114 9.216 12.288 18.432 24.576 96kHz 12.288 18.432 24.576 36.864 Unavailable 192kHz 24.576 36.864 Unavailable Unavailable Unavailable Table 1 Typical Relationships Between System Frequency and Sampling Rates.
HARDWARE CONTROL MODES
When the MODE pin is held low, the following hardware modes of operation are available.
MUTE AND AUTOMUTE OPERATION
In both hardware and software modes, pin 25 (MUTEB) controls selection of MUTE directly, and can be used to enable and disable the automute function, or as an output of the automuted signal. MUTEB PIN DESCRIPTION
0 Mute DAC channels 1 Normal Operation Floating Enable IZD, MUTEB becomes an output to indicate when IZD occurs. Table 2 Mute and Automute Control Figure 9 shows the application and release of MUTE whilst a full amplitude sinusoid is being played at 48kHz sampling rate. When MUTE (lower trace) is asserted, the output (upper trace) begins to decay exponentially from the DC level of the last input sample. The output will decay towards VMID with a time constant of approximately 64 input samples. When MUTE is deasserted, the output will restart almost immediately from the current input sample.
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1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2.5 0 0.001 0.002 0.003 Time(s) 0.004 0.005
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0.006
Figure 9 Application and Release of Soft Mute The MUTEB pin is an input to select mute or not mute. MUTEB is active low; taking the pin low causes the filters to soft mute, ramping down the audio signal over a few milliseconds. Taking MUTEB high again allows data into the filter. The automute function detects a series of zero value audio samples of 1024 samples long being applied to both channels. After such an event, a latch is set whose output (AUTOMUTED) is wire OR'ed through a 10kohm resistor to the MUTEB pin. Thus if the MUTEB pin is not being driven, the automute function will assert mute. If MUTEB is tied high, AUTOMUTE is overridden and will not mute unless the IZD register bit is set. If MUTEB is driven from a bi-directional source, then both MUTE and automute functions are available. If MUTEB is not driven, AUTOMUTED appears as a weak output (10k source impedance) so can be used to drive external mute circuits. Automute will be removed as soon as any channel receives a non-zero input. A diagram showing how the various Mute modes interact is shown below in Figure 10.
IZD (Register Bit) AUTOMUTED (Internal Signal) 10k MUTEB PIN SOFTMUTE (Internal Signal)
MUT (Register Bit)
Figure 10 Selection Logic for MUTE Modes
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INPUT FORMAT SELECTION
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In hardware mode, MLIIS (pin 28) and CSBIWO (pin 23) become input controls for selection of input data format type and input data word length. MLIIS 0 0 1 1 Table 3 Input Format Selection Note: In 24 bit I2S mode, any width of 24 bits or less is supported provided that LRCIN is high for a minimum of 24 BCKINs and low for a minimum of 24 BCKINs. ** This mode differs from the WM8716 which does 16-bit right justified in this mode. The previous mode is still available by using exactly 32 BCKIN per LRCIN cycle, 16 for left and right. This mode is automatically detected within the hardware and overrides the data width specified but not the format. CSBIWO 0 1 0 1 INPUT DATA MODE 24-bit right justified** 20-bit right justified 16-bit I2S 24-bit I2S
DE-EMPHASIS CONTROL
In hardware mode, MCDM1 (pin 27) and MDDM0 (pin 26) become input controls for selection of de-emphasis filtering to be applied. MCDM1 0 0 1 1 Table 4 De-emphasis Control Note: ** The actual de-emphasis within the WM8706 is the same for all data rates. This differs from WM8716 which has a different response for each sample rate. MDDM0 0 1 0 1 DE-EMPHASIS** Off 48kHz 44.1kHz 32kHz
SOFTWARE CONTROL INTERFACE
SELECTION OF CONTROL MODE
The WM8706 may be programmed to operate in hardware or software control modes. This is achieved by setting the state of the MODE pin. MODE 0 INTERFACE FORMAT Hardware Control Mode
Software Control Mode 1 Table 5 Control Interface Mode Selection
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3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE
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The WM8706 can be controlled using a 3-wire serial interface. MDDM0 is used for the program data, MCDM1 is used to clock in the program data and MLIIS is used to latch in the program data. The 3-wire interface protocol is shown in Figure 11.
MLIIS MCDM1
MDDM0
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Figure 11 3-Wire Serial Interface Notes: 1. B[15:9] are Control Address Bits 2. B[8:0] are Control Data Bits
REGISTER MAP
WM8706 uses a total of 4 programme registers, which are 16-bits long. These registers are all loaded through input pin MDDM0. After the 16 data bits are clocked in, MLIIS is used to latch in the data to the appropriate register. Table 6 shows the complete mapping of the 4 registers. B15 M0 M1 M2 M3
0 0 0 0
B14
0 0 0 0
B13
0 0 0 0
B12
0 0 0 0
B11
0 0 0 0
B10
0 0 1 1
B9
0 1 0 1
B8
UPDATEL UPDATER 0 IZD
B7
LAT7 RAT7 0 SF1
B6
LAT6 RAT6 0 SF0
B5
LAT5 RAT5 IW2 BCP
B4
LAT4 RAT4 IW1 REV
B3
LAT3 RAT3 IW0 0
B2
LAT2 RAT2 PWRDN ATC
B1
LAT1 RAT1 EEMPH LRP
B0
LAT0 RAT0 MUT I2S
ADDRESS Table 6 Mapping of Program Registers
DATA
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REGISTER ADDRESS A2, A1, A0 000 A2, A1, A0 DACL Attenuation 001 DACR Attenuation 010 DAC Control BITS LABEL DEFAULT DESCRIPTION
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[7:0] 8
LAT[7:0] UPDATEL
11111111 (0dB) 0
Attenuation data for left channel in 0.5dB steps. Attenuation data load control for left channel. 0: Store DACL in intermediate latch (no change to output) 1: Store DACL and update attenuation on all channels. Attenuation data for right channel in 0.5dB steps. Attenuation data load control for right channel. 0: Store DACR in intermediate latch (no change to output) 1: Store DACR and update attenuation on all channels. Left and right DACs soft mute control. 0: No mute 1: Mute De-emphasis control. 0: De-emphasis off 1: De-emphasis on Left and Right DACs Power-down Control 0: All DACs running, output is active 1: All DACs in power saving mode, output muted Audio data format select. Audio data format select. Polarity select for LRCIN/DSP mode select. 0: normal LRCIN polarity/DSP late mode 1: inverted LRCIN polarity/DSP early mode Attenuator Control. 0: All DACs use attenuations as programmed. 1: Right channel DACs use corresponding left DAC attenuations Output phase reverse. BCKIN Polarity 0 : normal BCKIN polarity 1: inverted BCKIN polarity De-Emphasis sample rate select. Infinite zero detection circuit control and automute control 0: Infinite zero detect disabled 1: Infinite zero detect enabled
[7:0] 8
RAT[7:0] UPDATER
11111111 (0dB) 0
0
MUT
0
1
DEEMPH
0
2
PWDN
0
[5:3] 011 Interface Control 0 1
IW[2:0] I2S LRP
000 0 0
2
ATC
0
4 5
REV BCP
0 0
[7:6] 8
SF[1:0] IZD
00 0
Table 7 Register Bit Descriptions
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ATTENUATION CONTROL
Each DAC channel can be attenuated digitally before being applied to the digital filter. Attenuation is 0dB by default but can be set between 0 and 127.5dB in 0.5dB steps using the 8 Attenuation control bits. All attenuation registers are double latched allowing new values to be pre-latched to both channels before being updated synchronously. Setting the UPDATE bit on any attenuation write will cause all pre-latched values to be immediately applied to the DAC channels. REGISTER ADDRESS A2, A1, A0 000 DACL Attenuation BIT LABEL DEFAULT DESCRIPTION
7:0
LAT[7:0]
11111111 (0dB) 0
Attenuation data for Left channel DACL in 0.5dB steps.
8
UPDATEL
Controls simultaneous update of all Attenuation Latches 0: Store DACL in intermediate latch (no change to output) 1: Store DACL and update attenuation on all channels. Attenuation data for Right channel DACR in 0.5dB steps.
001 DACR Attenuation
7:0
RAT[7:0]
11111111 (0dB) 0
8
UPDATER
Controls simultaneous update of all Attenuation Latches 0: Store DACR in intermediate latch (no change to output) 1: Store DACR and update attenuation on all channels.
Table 8 Attenuation Register Map Note: 1. 2. The UPDATE bit is not latched. If UPDATE=0, the Attenuation value will be written to the pre-latch but not applied to the relevant DAC. If UPDATE=1, all pre-latched values will be applied from the next input sample. Care should be used in reducing the attenuation as rapid large volume changes can introduce zipper noise.
DAC OUTPUT ATTENUATION
Registers LAT and RAT control the left and right channel attenuation. Table 9 shows how the attenuation levels are selected from the 8-bit words. XAT[7:0] ATTENUATION LEVEL 00(hex) dB (mute) 01(hex) 127.5dB : : : : : : FE(hex) 0.5dB FF(hex) 0dB Table 9 Attenuation Control Levels
MUTE MODES
Setting the MUT register bit will apply a 'soft' mute to the input of the digital filters: REGISTER ADDRESS 010 DAC Control Table 10 Mute Control BIT 0 LABEL MUT DEFAULT 0 DESCRIPTION Soft Mute select 0 : Normal Operation 1: Soft mute all channels
DE-EMPHASIS MODE
Setting the DEEMPH register bit puts the all the digital filters into de-emphasis mode: REGISTER ADDRESS 010 DAC Control BIT 1 LABEL DEEMPH DEFAULT 0 DESCRIPTION De-emphasis mode select: 0 : De-emphasis Off 1: De-emphasis On
Table 11 De-emphasis Control
WOLFSON MICROELECTRONICS LTD
PP Rev 1.2 April 2001 17
WM8706
POWERDOWN MODE
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Setting the PWDN register bit immediately connects all outputs to VMID and selects a low power mode. All trace of the previous input samples is removed, and all register settings are cleared. When PWDN is cleared again the first 16 input samples will be ignored as the FIR will repeat it's power-on initialisation sequence. REGISTER ADDRESS 010 DAC Control BIT 2 LABEL PWDN DEFAULT 0 DESCRIPTION Power Down Mode Select: 0 : Normal Mode 1: Power Down Mode
Table 12 Powerdown Control
DIGITAL AUDIO INTERFACE CONTROL REGISTERS
The WM8706 has a fully featured digital audio interface that is a superset of that contained in the WM8716. Interface format is selected via the IW[2:0] register bits in register M2 and the I2S register bit in M3. REGISTER ADDRESS BIT LABEL DEFAULT 000 DESCRIPTION Interface format Select
010 5:3 IW[2:0] DAC Control Table 13 Interface Format Controls REGISTER ADDRESS BIT LABEL I2S
DEFAULT 0
DESCRIPTION Interface format Select
011 0 Interface Control Table 14 Interface Format Control IW2 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 I2S 0 0 1 1 0 0 1 1 0 0 1 1 IW1 0 1 0 1 0 1 0 1 0 1 0 1 IW0
AUDIO INTERFACE DESCRIPTION ** 16 bit right justified mode 20 bit right justified mode 24 bit right justified mode 24 bit left justified mode 16 bit I2S mode 24 bit I2S mode 20 bit I2S mode 20 bit left justified (MSB first) mode 16 bit DSP mode 20 bit DSP mode 24 bit DSP mode 32 bit DSP mode 16 bit left justified mode
1 1 0 0 Table 15 Audio Data Input Format Note:
** In all modes, the data is signed 2's complement. The digital filters always input 24-bit data. If the DAC is programmed to receive 16 or 20 bit data, the WM8706 pads the unused LSBs with zeros. If the DAC is programmed into 32 bit mode, the 4 LSBs are ignored.
SELECTION OF LRCIN POLARITY
In left justified, right justified or I2S modes, the LRP register bit controls the polarity of LRCIN. If this bit is set high, the expected polarity of LRCIN will be the opposite of that shown in Figure 4, Figure 5 and Figure 6. Note that if this feature is used as a means of swapping the left and right channels, a 1 sample phase difference will be introduced. REGISTER ADDRESS 011 Interface Control BIT 1 LABEL LRP DEFAULT 0 DESCRIPTION LRCIN Polarity (normal) 0 : normal LRCIN polarity 1: inverted LRCIN polarity
Table 16 LRCIN Polarity Control WOLFSON MICROELECTRONICS LTD PP Rev 1.2 April 2001 18
WM8706
Product Preview In DSP modes, the LRCIN register bit is used to select between early and late modes: REGISTER ADDRESS 011 Interface Control BIT 1 LABEL LRP DEFAULT 0 DESCRIPTION DSP Format (DSP modes) 0 : Early DSP mode 1: Late DSP mode
Table 17 DSP Format Control In DSP early mode, the first bit is sampled on the BCKIN rising edge following the one that detects a low to high transition on LRCIN. In DSP late mode, the first bit is sampled on the BCKIN edge, which detects a low to high transition on LRCIN. No BCKIN rising edges are allowed between the data words. The word order is DIN left, DIN right.
ATTENUATOR CONTROL MODE
Setting the ATC register bit causes the left channel attenuation settings to be applied to both left and right channel DACs from the next audio input sample. No update to the attenuation registers is required for ATC to take effect. REGISTER ADDRESS 011 Interface Control BIT 2 LABEL ATC DEFAULT 0 DESCRIPTION Attenuate Control Mode: 0 : Right channels use Right attenuation 1: Right Channels use Left Attenuation
Table 18 Attenuation Control Select
OUTPUT PHASE REVERSAL
The REV register bit controls the phase of the output signal. Setting the REV bit causes the phase of the output signal to be inverted. REGISTER ADDRESS 011 Interface Control BIT 4 LABEL REV DEFAULT 0 DESCRIPTION Analogue Output Phase 0: Normal 1: Inverted
Table 19 Output Phase Control
BCKIN POLARITY
By default, LRCIN and DIN are sampled on the rising edge of BCKIN and should ideally change on the falling edge. Data sources which change LRCIN and DIN on the rising edge of BCKIN can be supported by setting the BCP register bit. Setting BCP to 1 inverts the polarity of BCKIN to the inverse of that shown in Figure 4, Figure 5, Figure 6, Figure 7 and Figure 8. REGISTER ADDRESS 011 Interface Control BIT 5 LABEL BCP DEFAULT 0 DESCRIPTION BCKIN Polarity 0 : normal BCKIN polarity 1: inverted BCKIN polarity
Table 20 BCKIN Polarity Control
DE-EMPHASIS SAMPLE RATE SELECTION
The SF[1:0] bits are used to select the de-emphasis rate. REGISTER ADDRESS 0011 Interface Control BIT 7:6 LABEL SF[1:0] DEFAULT 00 DESCRIPTION ** De-Emphasis Sample Rate Selection 00 : De-Emphasis Off 01: 48kHz 10: 44.1kHz 11: 32kHz
Table 21 De-emphasis Control Note: ** There is only one internal de-emphasis mode optimised for 44.1kHz. This is in contrast to WM8716 which is individually optimised for each sample rate.
WOLFSON MICROELECTRONICS LTD
PP Rev 1.2 April 2001 19
WM8706
INFINITE ZERO DETECTION
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Setting the IZD register bit determines whether the device is automuted when a sequence of more than 1024 zeros is detected. REGISTER ADDRESS 011 Interface Control BIT 8 LABEL IZD DEFAULT 0 DESCRIPTION Infinite zero detection circuit control and automute control 0: Infinite zero detect disabled 1: Infinite zero detect enabled
Table 22 IZD Control
DIGITAL FILTER CHARACTERISTICS
PARAMETER Passband Edge Passband Ripple Stopband Attenuation Table 23 Digital Filter Characteristics SYMBOL TEST CONDITIONS -3dB f < 0.444fs f > 0.555fs -60 MIN TYP 0.487fs 0.05 dB dB MAX UNIT
DAC FILTER RESPONSES
0.2 0 0.15 -20 0.1
Response (dB) Response (dB)
-40
0.05 0 -0.05 -0.1
-60
-80
-100
-0.15 -0.2 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5
-120
Figure 12 DAC Digital Filter Frequency Response - 44.1, 48 and 96kHz
0
Figure 13 DAC Digital Filter Ripple - 44.1, 48 and 96kHz
0.2
0 -20
Response (dB) Response (dB)
-0.2
-40
-0.4
-60
-0.6
-0.8 -80 -1 0 0.2 0.4 0.6 Frequency (Fs) 0.8 1 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5
Figure 14 DAC Digital Filter Frequency Response - 192kHz
Figure 15 DAC Digital Filter Ripple - 192kHz
WOLFSON MICROELECTRONICS LTD
PP Rev 1.2 April 2001 20
WM8706
Product Preview
DIGITAL DE-EMPHASIS CHARACTERISTICS
0 1 0.5 -2 0
Response (dB) Response (dB)
-4
-0.5 -1 -1.5 -2
-6
-8 -2.5 -10 0 2 4 6 8 10 Frequency (kHz) 12 14 16 -3 0 2 4 6 8 10 Frequency (kHz) 12 14 16
Figure 16 De-Emphasis Frequency Response (32kHz)
0
Figure 17 De-Emphasis Error (32kHz)
0.4 0.3
-2 0.2
Response (dB) Response (dB)
-4
0.1 0 -0.1 -0.2
-6
-8 -0.3 -10 0 5 10 Frequency (kHz) 15 20 -0.4 0 5 10 Frequency (kHz) 15 20
Figure 18 De-Emphasis Frequency Response (44.1kHz)
0
Figure 19 De-Emphasis Error (44.1kHz)
1 0.8
-2
0.6 0.4
Response (dB)
-4
Response (dB)
0.2 0 -0.2 -0.4
-6
-8
-0.6 -0.8
-10 0 5 10 15 Frequency (kHz) 20
-1 0 5 10 15 Frequency (kHz) 20
Figure 20 De-Emphasis Frequency Response (48kHz)
Figure 21 De-Emphasis Error (48kHz)
WOLFSON MICROELECTRONICS LTD
PP Rev 1.2 April 2001 21
WM8706
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RECOMMENDED EXTERNAL COMPONENTS
DVDD 8 + C1 C2 7 DGND 23 28 CSBIWO MLIIS MCDM1 MDDM0 MUTEB VOUTR 13 C6 DGND AGND VREFN 14 19 DVDD AVDD VREFP 15 20
AVDD
+ C3 C4 C5
AGND
Software I/F or Hardware Control
27 26 25
Software/hardware control mode select
24
MODE
WM8706
VOUTL 16
C7
AC-Coupled VOUTR/L to External LPF
+ +
1 5
LRCIN XTI BCKIN DIN
Audio Serial Data I/F
3 2
21
ZERO
VMID
18 + C8 C9
AGND Notes: 1. AGND and DGND should be connected as close to the WM8706 as possible. 2. C2, C3, C4 and C8 should be positioned as close to the WM8706 as possible. 3. Capacitor types should be carefully chosen. Capacitors with very low ESR are recommended for optimum performance.
Figure 22 External Components Diagram
RECOMMENDED EXTERNAL COMPONENT VALUES
COMPONENT REFERENCE C1 and C5 C2 to C4 C6 and C7 C8 C9 SUGGESTED VALUE 10F 0.1F 10F 0.1F 10F DESCRIPTION De-coupling for DVDD and AVDD/VREFP De-coupling for DVDD and AVDD/VREFP Output AC coupling caps to remove midrail DC level from outputs. Reference de-coupling capacitors for VMID pin.
Table 24 External Components Description
WOLFSON MICROELECTRONICS LTD
PP Rev 1.2 April 2001 22
WM8706
Product Preview
RECOMMENDED ANALOGUE LOW PASS FILTER (OPTIONAL)
4.7k 4.7k
+VS
_
51 10uF 1.8k 7.5K
+
+
1.0nF 47k 680pF -VS
Figure 23 Recommended Low Pass Filter (Optional)
WOLFSON MICROELECTRONICS LTD
PP Rev 1.2 April 2001 23
WM8706
Product Preview
PACKAGE DIMENSIONS
DS: 28 PIN SSOP (10.2 x 5.3 x 1.75 mm) DM007.C
b
28
e
15
E1
E
1
D
14
GAUGE PLANE
0.25 c A A2 A1 L
-C0.10 C
SEATING PLANE
Symbols A A1 A2 b c D e E E1 L REF: MIN ----0.05 1.62 0.22 0.09 9.90 7.40 5.00 0.55 o 0
Dimensions (mm) NOM --------1.75 --------10.20 0.65 BSC 7.80 5.30 0.75 o 4 JEDEC.95, MO-150
MAX 2.0 ----1.85 0.38 0.25 10.50 8.20 5.60 0.95 o 8
NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM. D. MEETS JEDEC.95 MO-150, VARIATION = AH. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
WOLFSON MICROELECTRONICS LTD
PP Rev 1.2 April 2001 24

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